The present invention relates to static random access memories (“SRAMs”), and more particularly to SRAMs having circuits for altering a supply voltage level or low voltage reference thereto. In addition, aspects of the invention relate to methods of operating an SRAM in which a supply voltage level or low voltage reference thereto is altered during write operation.
SRAMs are uniquely suited to the functions they serve within processors and other devices for storage of data to which fast (low cycle time) and ready (low latency) access is desired. Certain types of storage within processors are almost always implemented using SRAMs, such as cache memories, control stores, buffer memories, instruction pipelines and data pipelines including input output interfaces and buffers for direct memory access (“DMA”) interfaces. In addition, certain storage used for communication interfaces, e.g., network adapter buffers and so on, also utilize SRAMs for speed and low latency. Since SRAMs are frequently incorporated into chips on which other functions are implemented, e.g., processors (also referred to variously as microprocessors and central processing units (“CPUs”)), they must perform at operating conditions as difficult as those that the processors must tolerate. In particular, SRAMs must perform within the same broad range of operating temperatures as processors and must be capable of tolerating fluctuations in supply voltages, e.g., noise disturbance, to the same extent as processors. Moreover, the sizes of SRAMs and SRAMs incorporated into chips having other functions are increasing. It is not uncommon for SRAMs to reach hundred million capacity or greater, even those which are incorporated into other chips such as processors. In addition, to satisfy a growing demand for application specific integrated circuits (“ASICs”), it is desirable to provide SRAM macros (“macros” being functional modules) with large capacities capable of incorporation into multi-function chips, despite the scaling of the transistors and voltages used therein to unprecedented small sizes and values.
Storage cells in an SRAM or “SRAM cells” are arranged in an array of SRAM cells or “SRAM array.” Wordlines run in a direction of rows across an SRAM array. Bitlines run in a direction of columns across the SRAM array. Typically, one wordline is connected to each SRAM cell of a row of SRAM cells in the SRAM array. Typically, two bitlines carrying complementary signals are connected to each SRAM cell in a column of SRAM cells in the SRAM array, with one of the bitlines carrying a “true” signal representing the actual state of a bit signal and the other bitline carrying a “complementary” signal representing an inverted version of the bit signal.
As the size of each storage cell or “cell” within the SRAM array decreases with later generations of SRAMs, the threshold voltage of field effect transistors (“FETs”) used in each SRAM cell is subject to increased variability. In addition, the voltage level at which power is supplied to the SRAM array is reduced or “scaled” with the introduction of new generations of SRAMs. Design constraints may also require the number of SRAM cells in each column or row to increase.
The increased variability of the threshold voltage of the FETs of SRAM cells and the reduced power supply voltage level make it harder to guarantee that certain margins of error are maintained during operation of the SRAM. Such margins of error have a direct bearing on the SRAM's ability to maintain the integrity of the data stored therein. Clearly, there is a requirement that an extremely small proportion of such errors occur during operation of an SRAM. The maximum tolerable error or upper limit for such error is often measured in terms of a number of “sigma”, sigma representing the standard deviation in a distribution curve representing the occurrence of such errors. As currently manufactured SRAMs can have many millions of cells per SRAM array, the upper limit typically is set at one or two errors per the SRAM array. Stated another way, the maximum tolerable rate of error can be set at a level such as one or two failures per the entire SRAM, or one or two failures per 100 M, for example, where M denotes the number obtained by multiplying 1024 by itself or 1,048,576. This rate of error translates approximately to 5.2 sigma.
Margins of error which need to be maintained in the SRAM include access disturb margin (“ADM”) and write margin (“WRM”). The state of a bit stored in an SRAM cell is more likely to undergo a spontaneous inversion when the SRAM cell is partially selected. ADM pertains to the likelihood that the state of a bit stored in a partially selected cell of the SRAM array will spontaneously change from one state to another, e.g., flip from a “high” to a “low” state when a cell of the SRAM is accessed during a read or write operation. The unselected SRAM cell is “half” selected when a wordline connected to the SRAM cell has been activated, e.g., when one SRAM cell connected to that wordline is accessed for either a read or a write operation. Those “half” selected cells are more susceptible to access disturbs since the cells are to be disturbed even when they are not being accessed.
Another margin of error that must be satisfied is the ability to write the state of bit to an SRAM cell, given the strength of the bitline signals supplied to the SRAM cell and the time allotted to do so. Here, it is important that the SRAM cell have sufficient drive current to change from one stable state to another state under the influence of the bitline signals supplied thereto. If the SRAM cell fails to be written with the bit that is provided thereto, data integrity is impacted. WRM pertains to the occurrence of this type of error. Here again, it is important to reduce this type of error to an extremely miniscule amount. WRM, like ADM is typically measured in terms of standard deviations or “sigma” from a center of a distribution of the occurrence of error. As in the above case, WRM should preferably be maintained at a high sigma number, preferably at a sigma value of about 5.2 or more.
The scaling of one or more voltages supplied to each SRAM cell of the SRAM array for each succeeding generation of SRAMs only increases the difficulty of achieving a desired ADM and desired WRM. Various approaches have been suggested for providing high ADM, despite the scaling of the voltages. Increasing the magnitude of the threshold voltage of each n-type FET (“NFET”) and p-type FET or (“PFET”), i.e., raising the NFET threshold voltage and reducing the PFET threshold voltage helps improve ADM. Such practice improves ADM because each SRAM cell changes state only when a greater change occurs in voltages on the bitlines which is capable of exceeding a higher magnitude threshold voltage of one or more devices within the SRAM cell. However, such approach potentially worsens WRM. In an SRAM in which the available amount of drive current within each SRAM cell is already limited because of the scaling of the voltage, increasing the magnitude of the NFET and PFET threshold voltages makes the writing of each SRAM cell more difficult than before.
Moreover, whether or not the threshold voltage of the NFETs is raised or that of the PFETs is lowered, ADM and WRM tend to respond differently to temperature. The sigma value of ADM tends to be higher at lower temperatures, e.g., when a chip containing an SRAM is first turned on or when the chip is running at lower frequency. On the other hand, the sigma value of ADM becomes lower with increasing temperature. The sigma value of WRM may be lower at lower temperatures, and the sigma value of the WRM may become higher with increasing temperature. As transistor sizes are scaled further downward in future generations of SRAMs, it becomes more difficult to achieve desirable sigma values on both ADM and WRM over the range of temperatures in which SRAMs (and processors which incorporate them) are required to operate.
Providing a write scheme for an SRAM cells having PFET passgates is one goal featured in commonly assigned U.S. Pat. No. 6,549,453 to Wong. In one described scheme, a voltage provided to a memory cell is adjusted from one level to another during a data writing operation to the memory cell. Circuits are provided which allow a power supply voltage to pull-up devices of the memory cell to “float down” to a lower level during the data writing operation. In addition, in one or more other schemes described therein, pull-down devices of the memory cell are disconnected from ground and allowed to “float up” to a voltage level higher than ground.
Commonly assigned U.S. Patent Publication No. 2007/0121370 to Ellis et al. also describes methods in which a voltage provided to a memory cell is adjusted from one level to another when writing data to a memory cell. In the face of further scaling of the transistors and voltages used in SRAM cells, new ways are needed to maintain high WRM and ADM in SRAMs.
As the number of SRAM cells per column increases, it is becoming increasingly difficult to alter a voltage at which is supplied to a column of cells in a given amount of time.